Miniturization: Moore's Law revisited

[Terry Yager]

I remember reading somewhere, several years ago, that miniturization of electronic components (in silicon) had reached it's peak, and that no furthur miniturization would be possible using then-current technology. (The theory being that the light beam used to create the chip has a minimum width, i.e. one photon wide, and that chip technology had already reached the point where components were one photon-width away from one another).

Can anyone help me find any documentation of this theory?

Also, has there been a change in the technology since then? Are we doing things differently now, to allow for more miniturization, or are we just making the chip bigger to allow for the addition of more components?

--T

[Terry Yager]

I just love it when I cn answer my own question (I think). They increase chip density these days by adding more layers of substrate, (stacking) right? (Duh, I should have thought of this sooner).

--T

[mbbrutman]

I'm not a chip designer, but I follow this stuff ...

We can pack more on a chip because the feature size keeps shrinking. Features are the nuts and bolts - the gates that make up the registers, cache, logic units, etc. of a chip.

As feature size shrinks though a few problems are introduced:

- Voltage has to drop, or the electrons start punching holes through the very narrow paths they are supposed to follow.

- Etching techniques have to improve. Chips are basically made using photographic masks and etching chemicals. The smaller the feature size, the more detailed the masks have to be. You reach the point where normal light rays can't be used for the masks because the wavelength is too large. This leads to thinks like x-ray lithography.

- Life expectancy of the chip goes down. Silicon does age ...

- Pin count - the more function on a chip, the higher the pin count. (Probably.) Pins take up a lot of space and make timings more difficult ...


People really don't know what to do with the extra 'real estate'. A popular trick was to start adding caches right on the CPU chip. Another more recent trick was to put hardware multi-threading (or as Intel calls it, hyperthreading) on the chip. Some chips now are actually multi-processors on a chip, complete with two full CPU cores and some cache.

Stacking is another issue. All of those transistors are created by depositing multiple layers of substrate and and etching using multiple masks. It's error prone - all of the layers have to line up. Some of the RAM designers have done protoype RAM chips that are stacked more than usual to increase DRAM density.

For a good article on chip design check this out:

http://www.embedded.com/showArticle.jhtml?articleID=17501489

[Terry Yager]

Thanx for the link. The article is very informative, without being too technical.

--T