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About GilesGoat

Basic Information

About GilesGoat
Location:
Wales
Interests:
computers, hw developement, sw developement, VHDL, goats and such.
Occupation:
Working with an ox.

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130
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Last Activity
February 10th, 2012 03:11 AM
Join Date
December 11th, 2010
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Recent Entries

Documenting and rechecking.

by GilesGoat on May 4th, 2011 at 02:25 AM
So yesterday I had a bit of time again to work on this thing, to fight a bit also the "dentist's discomfort" I decided it was about time to recollet all the ideas and write them down so I began to write documentation about this thing ( was too tired to debug/check VHDL ).

It usually helps me because it's like "creating and checking a checklist again" of all the stuff done so far and in fact I found a couple of silly but fundamental things I forgot about I have

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Fixing things ..

by GilesGoat on May 2nd, 2011 at 01:40 PM
I had a little bit of a play with the thing ..

"amazing" how many silly little logic bugs you can make when you think a thing and you do another ..

Ok so after some test with the VHDL simulator ( ModelSIM, evaluation ) turns out a couple of signals had the wrong polarity, another wasn't totally correct, another was a simulator mistake ..

The "working UART" should ( still testing a few more things ) as that :

Code:

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De-Bugging

by GilesGoat on May 2nd, 2011 at 02:42 AM
So just to say had quite a few busy days, however I managed to continue to work a little bit ( a few hours ) on all this and found quite a few silly bugs.

The VHDL code as posted here does not do exactly what it should do there are various stupid errors there and there.

However when I'll have it fixed I'll post the results once done, reason I did not put yet any pics of the schematics as promised is because it's a bit of a pain to print them out which reminds me I should

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The project so far.

by GilesGoat on April 30th, 2011 at 03:22 AM
So let's talk now about the status of the project.

The status of the project is that yesterday night I finished re-checking everything and tried to create "the netlist" and see what was coming out, after a bit of a battle with some missing footprints, a couple of mis-labellings and a silly thing I got nuts for over 30 mins to find out about a strange error I was getting.

Turns out when I made the component "T11 CPU" I accidentally ( cut & paste

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An ongoing T-11 project.

by GilesGoat on April 30th, 2011 at 01:59 AM
So I decided to try to use this blog facility as a place to keep a bit of track/history of what is actually now became "the T-11 project", I think we are going maybe a bit too off topic from the thread that started it all so I think a blog could be a better place to continue it.

But first of all a little story about how all this started.

Well I could begin with "I always heard of PDP computers but I never seen/touched one" .. and this enough could

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