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Thread: XT-IDE Hardware Setup Gallery

  1. #11
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    I finally put together the XTIDE. This was a junk-box project--nothing was purchased except for the blank PCB itself. There's a strange mix of logic (LS and HC, depending on what I had on hand) and some ICs (check the LS138 and LS04 at the top of the card) are older than the IBM PC (the LS138 has a 1980 date code; the LS04, 1981.) I also used a AMD Am2764 (circa 1984) EPROM--I don't have any 2864 EEPROM on hand, but I've got scads of EPROMs. The bracket was constructed by bending a piece of sheet metal, drilling and tapping a pair of 4-40 holes for the PCB and riveting the bracket to blank bracket.

    So here's a photo.

    CGXTIDE.jpg

    Note that I replaced the bypass cap C8 with a 3-pin header, with the middle pin removed. C8's actually soldered to the back side of the PCB on the header pins. This lets me take power right from the PCB instead of having to fuss with power cables.

    Performance testing was interesting. Even though what's inserted is an ancient (circa 1999) Toshiba 192MB CF card, it substantially outscored a conventional 8GB IDE drive using Norton SI. Looking at the activity LED tells the story--the IDE drive is losing lots of revs, while the CF obviously doesn't have the problem.

    Okay, benchmark numbers. With the WD 8GB IDE drive, Norton SI stayed at 1.2, regardless of 4.77MHz or 8MHz turbo mode. With the 192MB CF card, the scores were 1.4 and 2.3, respectively. That tells me that the XTIDE is essentially CPU-bound reading CF drives.

    Without going to something like DMA transfer, I think I can hack the card slightly and improve performance by a factor of 2 or more for CF cards.

    What it will do with regular IDE drives is anyone's guess. However, it may be possible to fix the IDE drive performance with a software interleave--the down side is that you won't be able to read the drive in anything but an XTIDE that's been set up the same way as the original.

    However, I'll need to make software patches to the XTIDE BIOS also. Right now, I'd like a simple one that's easy to deal with; not the general-purpose-do-everything-for-everybody IDE Universal BIOS. Hargle, do you have the source to the old BIOS kicking around? I suppose that I could write one of my own, but that would be a lot of useless wasted effort.

  2. #12
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    Hi Chuck! Please try swapping the address lines around. You may be able to get the IO ports to become adjacent (LOHI) and then be able to use better software transfer methods.

    We are working on a new and improved Dual DMA IDE board for the N8VEM project. I am not sure when this will be done but hopefully soon. Unfortunately as a result of the ice storm last week the family internet connection is still severely degraded so that is messing things up for the next few days.

    Thanks and have a nice day!

    Andrew Lynch

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    Hi Andrew,

    Thanks, that's what I'll try first. My hope is that the parts to the original not be altered or changed. This would also be easily manageable with the CPLD version by simple reprogramming of the CPLD.

    --Chuck

  4. #14
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    Quote Originally Posted by Chuck(G) View Post
    I finally put together the XTIDE. This was a junk-box project--nothing was purchased except for the blank PCB itself. There's a strange mix of logic (LS and HC, depending on what I had on hand) and some ICs (check the LS138 and LS04 at the top of the card) are older than the IBM PC (the LS138 has a 1980 date code; the LS04, 1981.) I also used a AMD Am2764 (circa 1984) EPROM
    That was a question that I had as well, Can I mix HC/HCT and LS logic interchangeably, as long as the pinout is the same? Will there be any ill effects? The thought of pulling some of this stuff off of some old cards I have laying about appeals to my thrifty Scotch-Irish side. (read cheap SOB)

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    Quote Originally Posted by dpatten View Post
    That was a question that I had as well, Can I mix HC/HCT and LS logic interchangeably, as long as the pinout is the same? Will there be any ill effects? The thought of pulling some of this stuff off of some old cards I have laying about appeals to my thrifty Scotch-Irish side. (read cheap SOB)
    Of course you can mix HCT and LS families--that's one of the reasons that HCT exists. Mixing HC can get a little iffy depending on the circui. The big issue is that an HC logic "high" input level is about 3.5V, while an LS and HCT logic "high" input level is about 2.0V. So, if your're driving a bunch of inputs from the same line, HC may not work--but you can get around that by adding a pullup to the HC input.

    HC logic works over a wide range of power supply levels; in particular, it's happy as can be at 3.3V, while the same is not true of HCT or LS.

    Fortunately, the XTIDE design is fairly conservative, so HC/HCT/LS logic should work just fine. I had some Fairchild 74F573s (somewhat akin to 74ALS logic) and even they worked fine, even if their speed was overkill for the application.

    LSTTL family logic really is obsolete; HC and to some extent, HCT logic should be the target for new designs.

  6. #16
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    Hey Andrew,

    I think I may have a simpler modification--simply swap A0 and A3 on everything but the PROM. This makes the I/O port addressing a little strange, but it gets the job done. For example, if you're using a base address of 300H, the address of low-order byte of the data register would be 300H, the high-order 301H, the error register would be 308H; the sector count, 302H, the sector number, 30AH, and so on.

    So we'd still get the right low-byte/high-byte pairing at consecutive addresses for the data register.

    I've got to look at the PCB to see if there's an easy way to do the swap...

  7. #17
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    Hi Chuck! Well try it and see if it works! Nothing sells a good idea like a working prototype!

    I don't think a LOHI IO port arrangement is enough by itself to support DMA but it would be a good start and simplify the driver I think.

    Thanks and have a nice day!

    Andrew Lynch

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    Hi Andrew,

    No, LO-HI isn't enough to support DMA. but I have other ideas for that, in case the PIO is still too slow.

    The basic idea is that to read a sector, you currently use the following code, entering with CX=256 for a 512 byte sector:

    Code:
    readLoop:
                    in      al, dx                  ; get lower half
                    mov     ah, al
                    or      dx, 8                   ; switch to 2nd data reg
                    in      al, dx
                    and     dx, NOT 8               ; switch back
                    xchg    ah, al
                    stosw                           ; save it
                    loop    readLoop
    Which amounts to 8 instructions and 17 instruction bytes per word. If you shuffle the ports around a bit, as I described, then the code to read a 512 byte sector becomes something like this, entering with CX=128:

    Code:
    MoreData: 
           in      ax,dx
            stosw           ; read and store a word
            in      ax,dx
            stosw           ; word 2
            in      ax,dx
            stosw           ; word 3
            in      ax, dx
            stosw          ; word 4
            loop    MoreData
    Which transfers 4 words in 9 instructions (10 instruction bytes) by letting the 8088's BIU do the byte shuffling work. My guess is that this will be at least 2-3 times faster.

    At any rate, Hargle's sent me his code and I've re-assembled it and burned it so at least I know that it works. Now to stare at PCB traces and get the old X-acto knife out...

  9. #19
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    UPDATE 2/13/11 I swapped A0 and A3 and modified Hargle's BIOS slightly by changing the I/O port definitions and then substituting the PIO code detailed above. On boot, the code correctly identifies the IDE drive, but won't do sector I/O it (fails with a timeout). The fact that the drive information from the IDENTIFY command is being read correctly is a good sign, however.

    Looking at the BIOS code, there are some fixups needed--to fix the use of stuff like this:

    Code:
                    mov     dx, cs:[settings.ioBasePort]     ; data register
                    add     dx, IDE_SECTOR_COUNT_REG
                    mov     al, cl                  ; sectopr count
                    out     dx, al                  ; # of sectors to work on
                    inc     dx                      ; LBA low
                    pop     ax
    
                    out     dx, ax                  ; out LBA low+mid
                    add     dx, 2
                    mov     al, bl
                    out     dx, al                  ; LBA high
    
                    inc     dx
                    in      al, dx
                    and     al, SLAVE               ; keep device #
                    or      al, LBA
                    and     bh, 0fh
                    or      al, bh
                    out     dx, al                  ; out device + upper LBA
    
                    inc     dx                      ; command reg
                    mov     al, ch
                    out     dx, al
    With the new code, doing INC and constant arithmetic on the port number is a no-no! (it's not good coding practice anyway). Symbolic port references only (they're not consecutive any more)! So, hopefully, after I've located and fixed all of those, it'll take off and work.

  10. #20
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    Okay, what the heck, just after midnight, nothing on the one-eyed monster (who the heck actually looks at the Grammy awards, anyway?), so I figured I'd take a stab at the code.

    Success.

    With the new code, the Norton 4.5 SI numbers stack up this way:

    8GB Maxtor 91531U3 IDE drive: CPU: 4.77MHz SI =1.0 Disk SI = 6.3
    8GB Maxtor 91531U3 IDE drive: CPU: 8.00MHz SI =1.7 Disk SI = 6.4

    192MB Toshiba CF card: CPU: 4.77MHz SI=1.0 Disk SI = 6.1
    192MB Toshiba CF card: CPU: 8.00MHz SI=1.0 Disk SI = 6.3

    That's close to a 6x improvement on the disk and 4-5 on the CF.

    I don't think CPU speed is a factor any longer at least for these devices. And I suspect that DMA would actually be slower.

    The mod was pretty simple--I cut the A0 and A3 traces at each via (near the edge connector) on the wiring side of the PCB and just ran two wires soldered from said vias to the appropriate 74LS138 pins.

    The swap shouldn't matter with the ROM unless you're using an externally-programmed EPROM like me. In that case, use the following C program to swap the bytes around in the BIOS image file before programming:

    Code:
    #include <stdio.h>
    #include <stdlib.h>
    #include <string.h>
    
    #define K_TO_SHUFFLE 8
    
    #define BYTES_TO_SHUFFLE (K_TO_SHUFFLE * 1024)	// self-explanatory
    
    //  Program to shuffle data addressed by interchange A0 and A3 lines.
    //  -----------------------------------------------------------------
    //
    //    Done originally for the XTIDE modifications, but may find some
    //    other application.
    //
    //    Re-arranges bytes such that:
    //
    //	0123456789abcdef -> 082a4c6e193b5d7f
    //
    //    Chuck Guzis, February, 2011.
    //
    
    void main( int argc, char *argv[])
    {
    
      FILE
        *in,
        *out;				// input and output FDs
    
      unsigned char
        image[ BYTES_TO_SHUFFLE],		// shuffler
        temp;				// temporary byte
    
      int
        i, j, k;				// scratch integers
    
    
      printf( "\nROM A0-A3 swap data shuffler (%dKiB version)\n", K_TO_SHUFFLE);
      if ( argc != 3)
      {
        fprintf( stderr, "\nCommand syntax is %s <input-file> <output-file>\n",
          argv[0]);
        exit(-1);				// quit after giving summary
      } // if improper number of arguments
    
      in = fopen( argv[1], "rb");
      if ( !in)
      {
        fprintf( stderr, "\nERROR - Could not open input file %s\n", argv[1]);
        exit(1);
      } // if input won't open
    
      out = fopen( argv[2], "wb");
      if ( !in)
      {
        fprintf( stderr, "\nERROR - could not open output file %s\n", argv[2]);
        exit(2);
      } // if output won't open
    
      memset( image, 0, BYTES_TO_SHUFFLE);	// clear buffer
      k = fread( image, sizeof( unsigned char), BYTES_TO_SHUFFLE, in);
      if ( k != BYTES_TO_SHUFFLE)
        fprintf( stderr, "\nWAarning - Short read; buffer padded with zero.\n");
      fclose( in);
    
    //  Do the shuffle.
    
      for ( i = 0; i < BYTES_TO_SHUFFLE; i += 16)
      {
        for ( j = 1; j < 8; j +=2)
        {
          temp = image[ i+j];
          image[i + j] = image[ i+j+7];
          image[i+j+7] = temp;		// swap 4 pairs of bytes
        } // swap odd-numbered bytes
    
      } // shuffle in 16-byte blocks
    
      k = fwrite( image, sizeof( unsigned char), BYTES_TO_SHUFFLE, out);
      fclose( out);
    
      if ( k != BYTES_TO_SHUFFLE)
      {
        fprintf( stderr, "\nError - Write error; only %d of %d bytes written\n.",
          k, BYTES_TO_SHUFFLE);
        exit(10);
      } // if short write
    
      printf( "\nAll done.\n");
      exit(0);
    
    }  // end of main
    Enjoy!

    P.S. Attached are the "un-swapped" and "swapped" BIOS images that I used.
    Attached Files Attached Files
    Last edited by Chuck(G); February 14th, 2011 at 07:17 PM.

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